The present invention relates to a memory tester for testing, for example, memories fabricated as semiconductor integrated circuits and, more particularly, to an address generating device for use in such a memory tester.
FIG. 1 shows the basic construction of a conventional memory tester in its entirety. The memory tester comprises a timing generation part 10, a pattern generator 20, a waveform formatter 30 and a logical comparison part 40 and tests a memory M. The parts 10, 20, 30 and 40 are connected to a central processing unit (i.e. a computer) (not shown) via a system bus to conduct an initialization for test and to make an analysis of test results. Based on a reference clock CK available from the timing generation part 10, the pattern generator 20 generates an address signal ADS, test pattern data TPD and a control signal CS which will ultimately be applied to the memory under test M. The address signal ADS, the test pattern data TPD and the control signal CS are provided to the waveform formatter 30.
The waveform formatter 30 derives from the test pattern data TPD a test pattern signal which has a waveform necessary for test, and applies the test pattern signal TPD to the memory under test M together with the address signal ADS and the control signal CS. The memory under test M is placed under control of the control signal CS for write and read of the test pattern signal. The logical comparison part 40 compares expected value data ED from the pattern generator 20 and data read out of the memory under test M and determines if the memory under test M is non-defective, depending on wether the both pieces of data match.
FIG. 2 shows the internal construction of the pattern generator 20, which is made up of an address generation part 20A, a test pattern data generation part 20B, a control signal generation part 20C and a sequence control part 20D for controlling the parts 20A through 20C.
The sequence control part 20D is comprised of an instruction memory 21 wherein there is stored a program composed of a series of instructions for controlling the sequence of memory testing, a program counter 22 for specifying an address of the memory 21 to be read out and a program counter controller 23 for controlling the program counter 22 on the basis of an instruction code read out of the memory 21. The memory area of each address in the instruction memory 21 includes an instruction code area 21A wherein an instruction code for controlling the program sequence is written, an address computation instruction area 21B wherein an address computation instruction is written, a data computation instruction area 21C wherein a data computation instruction is written, and a timing data area 21D wherein timing data for generating the control signal CS is written.
The output of the program counter 22 is provided as an address to the instruction memory 21, from which contents stored in the areas 21A, 21B, 21C and 21D of the address are simultaneously read out and provided to the program counter controller 23, the address generation part 20A, the test pattern data generation part 20B and the control signal generation part 20D. The program counter controller 23 decodes the instruction code read out of the instruction code area 21A and increments, decrements or holds the program counter 22, or loads therein the read-out address value.
The address generation part 20A has an address computation part 24 composed of an X address computation part 24X and a Y address computation part 24Y and responds to the address computation instruction read out of the address computation instruction area 21B of the instruction memory 21 to create an X address and a Y address through computation in the X address computation part 24X and the Y address computation part 24Y, respectively. The test pattern data generation part 20B and the control signal generation part 20C also operate in about the same manner as does the address generation part 20A and respond to the instructions read out of the data computation instruction area 21C and the timing data area 21D to generate the test pattern data TPD and the control signal CS. The pattern generator 20 of such a construction is disclosed in U.S. Pat. No. 4,797,886, for instance.
An address descrambler 25 converts address viewed from the outside of the semiconductor memory under test M (which address will hereinafter be referred to a logical address) to the corresponding address in the actual memory cell configuration (which address will hereinafter be referred to as a physical address). The address descrambler 25 is formed by a memory which has a translation table. Prior to a memory test a translation table for the memory under test M is loaded in the address descrambler 25 via a system bus (not shown). In the memory test the logical address produced by the address computation part 24 is provided as a read address to the descrambler 25 to read out therefrom the corresponding physical address.
FIG. 3 shows in more detail the internal construction of the address computation part 24 and the address computation instruction area 21B of the instruction memory 21 in a memory tester already put on the market. The address computation instruction area 21B comprises a data area 21BD wherein data for an address computation and command data described later on are described and a control signal area 21BC including control bits as signed to various control signals for controlling the execution of the address computation. The X address computation part 24X has such a construction as described below. A start address register 241 holds an initial value of the X address. A counter 242 responds to a preset control signal C1 to preset the contents of the start address register 241 and increments, decrements or holds the preset contents in response to an address computation control signal (1). A multiplexer 243 responds to a selection control signal S1 in the address computation instruction to provide the contents of either one of the counter 242 and a current register 244 to the one input of an arithmetic and logic unit 245. A register 246 holds an address shift initial values, which is loaded in a counter 247 in response to a preset control signal C2, and the counter 247 increments, decrements or holds the address shift initial value in response to a computation control signal (2). The contents of the counter 247 are provided to the other input of the arithmetic and logic unit 245. The arithmetic and logic unit 245 responds to an address computation control signal C3 to conduct a computation between the two input, for example, an addition, subtraction, ORing or ANDing, and stores the computed output in the current register 244. A multiplexer 248 responds to a selection control signal S2 in the address computation instruction to output the contents of either one of the counter 242 and the current register 244.
Data, described as a part of a microinstruction program in the data area 21BD in the address computation instruction area 21B of the instruction memory 21, is loaded into the registers 241 and 246 in accordance with load control signals L1 and L2. The operations of the counters 242 and 247, the arithmetic and logic unit 245 and the multiplexers 243 and 248 are controlled by control signals C1, C2, C3 and S1, S2 written in the control signal area 24BC in the address computation instruction area 21B. For example, when the counter 242 is selected by the multiplexer 242 and is incremented one by one, it is possible to obtain an X address pattern which increases one by one from its initial address value. By loading an address shift initial value into the counter 247 and putting it in the holding state, selecting the current register 244 by the multiplexer 243 and conducting an addition in the arithmetic and logic unit 245, an X address pattern is obtained in which the address increases by an address shift value each time. Alternatively, by causing the arithmetic and logic unit 245 to add a proper shift value of the counter 247 to or subtract it from an address specified by the counter 242, it is possible to arbitrarily access a memory cell in the vicinity of a certain cell of the memory under test M. Thus, various address patterns can be generated by appropriately applying control signals to the counters 242, 247, the multiplexers 243, 248 and the arithmetic and logic unit 245.
The Y address computation part 24Y is also identical in construction with the X address computation part 24X. A series of addresses for accessing the memory under test M are generated by the address generation part 20A including such X and Y address computation parts 24X and 24Y, and as is well-known in the art, the memory M is tested in a sequence of address patterns different for each different purpose of the test. The generation of such address patterns is disclosed in, for instance, U.S. Pat. No. 4,402,081.
In recent years, a flash memory has attracted attention as an nonvolatile memory which has a large-capacity and is capable of rewriting a number of times. The flash memory has a plurality of modes of operation such as read/write operation of data, an erasure of all of the data stored therein block by block, etc. These modes of operation are each selected by inputting a specific command into a controller in the memory from the outside. A terminal for inputting the command is not a dedicated terminal but is used also as an address terminal. The input to the terminal is switched between the address and the command by, for example, changing the logic of a control signal that is applied to a specific terminal of the flash memory.
In the test of such a memory M the command for controlling its mode of operation must be provided from the data area 21BD of the instruction memory 21 via the conventional address computation part 24X (or 24Y) shown in FIG. 3. In the prior art, for example, command data in the area 21BD is set in the register 246 and its value is loaded in the counter 247, after which the multiplexer 243 is put in a non-select state (providing no output) and the command data in the counter 247 is set in the current register 244 via the arithmetic and logic unit 245. Moreover, the multiplexer 248 is connected to the current register 244, from which the command data is provided to the memory under test M.
In the case where such an address is switched to the command in the middle of testing the memory M, it is necessary to subsequently return to the address at the point of switching. To perform this, it is necessary to provide a sequence of microinstruction steps in which the value of the counter 247 in a step necessary for switching from the address to the command in an instruction program is preknown, the register 246 is reset to an initial value, then the value is loaded in the counter 247 and the counter 247 is advance one by one to the preknown value.
During the execution of such a sequence of microinstruction steps for resetting the counter 247 to the value at the point of switching between the address and the command, no address is available from the address computation part 24X and the test of the memory M is suspended. That is, the memory M is in a dummy cycle during this time. In the actual use of the memory M, however, its operation does not include such a dummy cycle--this poses a problem that during the test the memory M does not operate in exactly the same way as in the actual use. In addition, it is cumbersome to prepare an instruction program in anticipation of the value of the counter 247 at the time of switching from the address to the command.
In the case of testing a semiconductor memory of the type using one input terminal both as the address input terminal and as the command input terminal as mentioned above, if the semiconductor memory is one that the logical address and the physical address do not always match, a translation table for translating the logical address to the physical address is prestored in the memory forming the address descrambler 25 and the logical address which is output from the address computation part 24 is translated to the physical address by use of the address translation table. This allows ease in the preparation of the microinstruction program for address generation use. It is necessary, however, that the memory tester also be capable of testing a memory of the type in which the logical address and the physical address match. To this end, an enable register and a multiplexer (both not shown) are provided and the output address from the descrambler 25 or the input address thereto is selectively output by the multiplexer in accordance with the contents of the enable register. Prior to the start of the test, an enable signal corresponding to the type of the memory under test M is set in the enable register via a system bus (not shown) and its contents cannot be changed in the course of the test. Hence, when a command for changing the mode of operation of the memory under test M is provided from the address computation part 24 in the middle of the test, the command is also translated by the descrambler 25, and consequently, no correct command can be provided to the memory M.